1. Field of the Invention
The present invention relates to a semiconductor device comprising a memory cell array having a bit line structure hierarchized using global bit lines and local bit lines, and a control method thereof.
2. Description of Related Art
In recent years, miniaturization of a memory cell array has been achieved in semiconductor devices such as DRAM, and thus in order to overcome a performance problem caused by an increase in the number of memory cells connected to a bit line, a configuration in which the bit lines are hierarchized into global bit lines and local bit lines has been proposed (for example, refer to Japanese Patent Application Laid-open No. 2008-262632 (U.S. Pat. No. 7,697,358 B2)). It is required to reduce memory cell size to, for example, 6F2 or 4F2 (“F” is minimum manufacturing scale), and the bit line pitch in this case needs to be'set to 2F that is a manufacturing limit. In general, when employing the hierarchical bit line structure, a plurality of global bit lines arranged with a predetermined pitch are alternately connected to a plurality of global sense amplifiers placed on both sides (both ends) thereof, and N local bit lines corresponding to N segments into which each global bit line is partitioned in its extending direction are arranged. Further, it is difficult to arrange sense amplifiers so that they adapt to the reduced bit line pitch, and therefore an arrangement in which a plurality of sense amplifiers are alternately arranged at both ends of the global bit lines is effective (so-called zigzag alignment).
However, even when employing the hierarchical bit line structure, it is inevitable that a ratio of coupling capacitance between adjacent bit lines to overall bit line capacitance increases by reducing the bit line pitch to around 2F. Then, coupling noise between the adjacent bit lines remarkably increases due to influence of the coupling capacitance between the adjacent bit lines that is combined with a reduction in memory cell capacitance of the memory cell. Accordingly, there arises a problem that when a signal voltage read out from a memory cell by selecting a word line is sensed and amplified by a sense amplifier, the coupling noise between the adjacent bit lines increases so that sensing margin of the sense amplifier decreases.